This requires the ability to both increment and decrement the counter, potentially on the same clock. In a synchronous FIFO design, one way to determine whether a FIFO is full or empty is to use separate count register to track the number of entries in the FIFO. Therefore, it is imperative to design them correctly from the beginning! This article describes one proven method to design an asynchronous FIFO. An almost correct design may function 99% of the time, but the 1% failure will cost you countless hours of debugging, or worse, a respin. An asynchronous FIFO refers to a FIFO where data is written from one clock domain, read from a different clock domain, and the two clocks are asynchronous to each other.Ĭlock domain crossing logic is inherently difficult to design, and even more difficult to verify. There are many known design methods to safely pass data asynchronously from one clock domain to another, one of which is using an asynchronous FIFO. Metastability and synchronization is an extremely complex topic that has been the subject of over 60 years of research. This article assumes knowledge of basic synchronous FIFO concepts. Please treat this as a concise summary of the design described his paper (specifically, FIFO style #1 with gray code counter style #2). What better way to relearn a topic than to write about it! Note that this asynchronous FIFO design is based entirely on Cliff Cumming’s paper Simulation and Synthesis Techniques for Asynchronous FIFO Design.

One of my first tasks after returning to work was to check over the RTL of an asynchronous FIFO in Verilog. Apology for the lack of updates, but I have been on a rather long vacation to Asia and am slowly getting back into the rhythm of work and blogging.

Fifo verilog code basic